Compilation Tools for Run-Time Recon gurable Designs

This paper describes a framework and tools for automating the production of designs which can be partially recon gured at run time. The tools include: (i) a partial evaluator, which produces con guration les for a given design, where the number of con gurations can be minimised by a process known as compile-time sequencing; (ii) an incremental con guration calculator, which takes the output of the partial evaluator and generates an initial con guration le and incremental conguration les that partially update preceding congurations; (iii) a tool which further optimises designs for FPGAs supporting simultaneous conguration of multiple cells. While many of our techniques are independent of the design language and device used, our tools currently target Xilinx 6200 devices. Simultaneous con guration, for example, can be used to reduce the time for reconguring an adder to a subtractor from time linear with respect to its size to constant time at best and logarithmic time at worst.